1. Field of the Invention
The embodiments of the invention generally relate to semiconductor-on-insulator (SOI) structures and, more specifically, to an SOI structure, such as an SOI field effect transistor (FET), having selectively placed sub-insulator layer void(s) and a method of forming the SOI structure.
2. Description of the Related Art
By providing a buried insulator layer between a semiconductor device layer and the semiconductor substrate, semiconductor-on-insulator (SOI) structures minimize parasitic capacitance between devices and the substrate as compared to bulk semiconductor structures. While it may be desirable to minimize capacitance coupling between some devices and the substrate, it may also be desirable to allow strong capacitance coupling between other devices and the substrate. For example, traditional single-gated CMOS devices can benefit from reduced substrate coupling, while double-gated or back-gated CMOS devices can benefit from enhanced substrate coupling, thereby allowing for the substrate to be used as the back gate. Furthermore, while it may be desirable to minimize capacitance coupling between one or more regions of a particular device (e.g., the source diffusion region, the drain diffusion region and/or the body contact diffusion region of an SOI field effect transistor (FET)) and the substrate, it may also be desirable to allow for strong capacitance coupling between another region of the same device (e.g., the channel region of the same SOI FET) and the substrate. This is the case, for example, in low or mixed frequency applications, such as phase locked loops (PLLs), and in other applications where diffusion-to-substrate capacitance is not depleted. Therefore, there is a need in the art for an SOI structure and an associated method of forming the SOI structure that provides for selectively adjusted capacitance coupling between different regions of the semiconductor layer and the substrate.